Разработка тестового файла для модуля apb_slave_controller

тестовый файл к коду module apb_slave_controller #( parameter int ADDR_WIDTH = 32, parameter int DATA_WIDTH = 32, parameter int NUM_REGIONS = 4 )( // --- APB Interface --- input logic pclk_i, input logic presetn_i, input logic [ADDR_WIDTH-1:0] paddr_i, input logic pwrite_i, input logic psel_i, input logic penable_i, input logic [DATA_WIDTH-1:0] pwdata_i, output logic pready_o, output logic [DATA_WIDTH-1:0] prdata_o, output logic pslverr_o, // --- Region Configuration Outputs --- output logic [ADDR_WIDTH-1:0] addr_baze_region0_o, output logic [ADDR_WIDTH-1:0] addr_end_region0_o, output logic encrypted_region0_o, output logic [ADDR_WIDTH-1:0] addr_baze_region1_o, output logic [ADDR_WIDTH-1:0] addr_end_region1_o, output logic encrypted_region1_o, output logic [ADDR_WIDTH-1:0] addr_baze_region2_o, output logic [ADDR_WIDTH-1:0] addr_end_region2_o, output logic encrypted_region2_o, output logic [ADDR_WIDTH-1:0] addr_baze_region3_o, output logic [ADDR_WIDTH-1:0] addr_end_region3_o, output logic encrypted_region3_o, // --- Control Signals --- output logic start_key_load_o, input logic keys_loaded_i, output logic load_data_o, input logic data_loaded_i, output logic start_read_o, input logic read_complete_i, input logic encryption_done_i, // REMOVED: regions_configured_i (Теперь считаем внутри) output logic reset_keys_o, output logic irq_o, output logic [3:0] state_o, output logic busy_o ); // --- Internal Signals --- logic [3:0] state, next_state; logic irq_pending; logic write_irq_clear; logic reset_keys_pulse; // Таймаут теперь здесь (последовательная логика) logic [15:0] timeout_counter; // --- APB Handshake --- logic apb_write; logic apb_read; logic [7:0] addr_aligned; logic addr_valid; logic start_process; logic abort_process; logic reset_keys_cmd; // --- Write Strobes --- logic [NUM_REGIONS-1:0] write_baze, write_end, write_cfg; // --- Internal Registers --- logic [ADDR_WIDTH-1:0] addr_baze_region [0:NUM_REGIONS-1]; logic [ADDR_WIDTH-1:0] addr_end_region [0:NUM_REGIONS-1]; logic encrypted_region [0:NUM_REGIONS-1]; logic all_configured; // --- Address Map (Word indices) --- localparam int REG0_BAZE_ADDR = 8'd0; localparam int REG0_END_ADDR = 8'd1; localparam int REG0_CFG_ADDR = 8'd2; localparam int REG1_BAZE_ADDR = 8'd4; localparam int REG1_END_ADDR = 8'd5; localparam int REG1_CFG_ADDR = 8'd6; localparam int REG2_BAZE_ADDR = 8'd8; localparam int REG2_END_ADDR = 8'd9; localparam int REG2_CFG_ADDR = 8'd10; localparam int REG3_BAZE_ADDR = 8'd12; localparam int REG3_END_ADDR = 8'd13; localparam int REG3_CFG_ADDR = 8'd14; localparam int CTRL_ADDR = 8'd16; localparam int STATUS_ADDR = 8'd17; localparam int IRQ_CLEAR_ADDR = 8'd18; localparam int MAX_REG_INDEX = 8'd18; // --- FSM States --- typedef enum logic [3:0] { ST_IDLE = 4'b0000, ST_CONFIG_CHECK = 4'b0001, ST_LOAD_KEYS = 4'b0010, ST_WAIT_KEYS = 4'b0011, ST_LOAD_DATA = 4'b0100, ST_WAIT_DATA = 4'b0101, ST_ENCRYPT = 4'b0110, ST_READ_RESULT = 4'b0111, ST_WAIT_READ = 4'b1000, ST_DONE = 4'b1001 } state_t; // --- APB Logic --- assign pready_o = 1'b1; // Упрощено для стабильности, можно вернуть проверку addr_valid assign apb_write = psel_i && penable_i && pwrite_i; assign apb_read = psel_i && penable_i && !pwrite_i; assign addr_aligned = paddr_i[7:2]; assign addr_valid = (addr_aligned <= MAX_REG_INDEX); assign pslverr_o = psel_i && !addr_valid; // --- Strobes --- genvar i; generate for (i = 0; i < NUM_REGIONS; i = i + 1) begin : gen_strobes assign write_baze[i] = apb_write && (addr_aligned == (i * 4)); assign write_end[i] = apb_write && (addr_aligned == (i * 4) + 1); assign w